This invention is related to U.S. Pat. No. 4,774,422, filed on May 1, 1987, by Darrel D. Donaldson, Richard B. Gillett, Jr., and Douglas D. Williams entitled "High Speed Low Pin Count Interface."
The present invention relates to the field of computer data buses generally and more specifically to high speed buses which allow bidirectional communication. In most buses, especially buses that contain multiple lines to transfer data in a parallel format, there are windows of time during which data on the bus is valid. In synchronous buses, periodically repeating cycles form the basis for timing of such buses and in each of those cycles windows are usually defined by a separate signal which becomes active once per bus cycle. During the time between windows, the data on the bus is allowed to change to new levels and is considered to be invalid.
In general, data communication on a bus involves a bus driver to place data onto the bus and a storage device to retrieve and store data from the bus. The bus driver, can generally be one of two types. One type can only drive a bus line to one level, e.g., to a ground potential, and thus requires a pull-up or precharging drives to establish the other bus level. The other type actively drive the bus line to both levels and does not require precharging or pull-up devices. When a drive signal controlling the bus driver is in one state, it enables the bus driver and causes the bus driver to drive the bus to a level (either the same or inverted) corresponding to input data at the input terminal of the bus driver. When the drive signal is in the other state, it disables the bus driver causing the bus driver to cease driving the bus. Immediately following the enabling of the bus driver, while the data on the bus is still changing, the data is also considered to be invalid. For each particular driver technology and interface characteristics, this data invalid time is relatively fixed, as it depends on conditions like bus length, bus driver propagation delay, etc. As bus frequencies increase, the cycle times of the bus decreases, and the bus driver enable time decreases correspondingly. Thus, the amount of the bus driver enable time during which data is valid also decreases.
The storage device responds to the actuation of a latch signal by storing the data currently on the bus. The latch signal must be timed so that the storage device stores data while it is still valid on the bus, and conventional practice is to time the latch signal so that the storage device stores data while the bus driver is still enabled. Thus the conventional drive signal continues to drive the bus for some "hold time" after the latch signal is actuated. Conventional practice for driving buses between sets of integrated circuit chips is to actuate the latch prior to disabling the bus driver because the voltage levels on the bus may be indeterminate when the bus is not being driven, and during such times the storage device may not actually store the data intended to be transferred over the bus from the bus driver.
Generation of the bus driver and latch signals to obtain the hold time requires two separate clock signals: one for the latch signal and one for the drive signal which extends beyond the latch signal. Those two clock signals, however, are only sufficient for unidirectional communication on the bus lines. Full bidirectional communication on the same bus lines requires two storage device/bus driver pairs, as well as four clock signals (two signals for each direction).
Furthermore, the drive signal used for communication in one direction on the bus must not overlap the drive signal used for communication in the other direction so that the bus drivers used for communication in each direction are not driving the bus simultaneously. If they do drive the bus simultaneously even for only a small amount of time because of clock skew, for example, then the drivers and the bus lines will experience current spikes, and the availability of the data transferred by the second drive signal will be delayed.
The generation of the multiple clocks for bidirectional communication is further complicated if that communication must be synchronized to an overall system clock. For example, if there were a system bus with its own bus timing coupled to one of the elements of the bus, then the four clock signals necessary for bidirectional communication would have to be synchronized with the timing of this system bus. Such synchronization ma be difficult for several reasons. First, the cycle time of the clock used for the system bus may be so small as to make it impractical to further subdivide the clock cycle time to obtain four different clock signals conforming to the requirements for bidirectional communication. Furthermore, even if it were possible to obtain those clock signals, their pulse widths may be so narrow that logic circuitry in the elements could not reliably respond to them.
One design approach would be to eliminate the need for the four separate clock signals by using two unidirectional buses, one for communication in each direction. The addition of another set of lines for the other unidirectional bus, however, doubles both the number of bus lines and the area which must be dedicated for those lines. In addition, the use of such buses doubles the number of pins on the components which couple to that bus. Thus, for example, to transfer 64 bits of data in parallel using two unidirectional buses would require an additional 64 pins per interface as compared to a single bidirectional bus.
Of all these disadvantages, the increased pin count may be the most severe. If the number of pins required exceeds the number that can be supported in a single integrated chip, then multiple chips must be used for the circuitry. This can be disadvantageous because circuitry generally operates more slowly when divided between multiple chips. Thus, the design of high speed circuitry frequently involves the development of techniques that minimize the required number of pins to avoid dividing functions across chip boundaries. Pin counts are often a limiting factor in circuit design because of limited space for those pins on printed circuit boards.
Another desirable design goal for a high speed bus interface between two buses, such as a dedicated user bus and a main system bus, is to place on the user bus a copy of all the communications on the main system bus. This allows circuitry coupled to the user bus to monitor the use of different resources on the main system bus. To meet this requirement, data must be transferred from the system bus to the user bus during each cycle of the system bus. If the user bus uses single lines for bidirectional communication, then that bus must operate twice as fast as the system bus to allow two communications (one each direction) during each cycle of the system bus cycles. This requirement further exacerbates the timing problems.
If the user bus can be synchronized with the system bus and reproduce the traffic on the system bus, including messages placed on the system bus from the user bus, several advantages are available. One advantage of this system is that one user of the system bus can monitor the system bus transactions of all the other users. For example, one user can ensure that its cache memories are valid by checking all the memory write operations of the other users. Users can observe their own system bus transactions in relationship to the system bus transactions of other users. In addition, users can send messages to themselves over the system bus to permit easy coordination of node resources, such as system bus control and status registers, that are accessible over the sytem bus.
Accordingly, it is an object of the present invention to minimize the number of clock signals needed for high speed bidirectional bus transfer without driver overlap.
Another object of the present invention is to provide high speed data transfer between two buses so that one bus can obtain a copy of all traffic on another bus.
Yet another object of the invention is to provide one bus with a return copy of the messages it sent to the other bus.
A still further object of the invention is to minimize the number of pins needed for an interface to a high speed system bus.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by the instrumentalities and combinations particularly pointed out in the appended claims.